Converter from delta modulation to pulse code modulation

ABSTRACT

A system for the conversion of a delta modulation ( Delta M) signal into a pulse code modulation (PCM) signal and vice versa. The system for the conversion of a Delta M modulation signal into a PCM modulation signal comprises: register means for storing an input signal consisting of n binary digits generated by a Delta M modulator during a time period corresponding to a normal PCM modulation sampling period Ti, each binary digit representing a positive or negative Delta M modulation quantization step of a quantized signal; means for effecting the algebraic sum of the positive and negative quantization steps to obtain the increase or decrease of the quantized signal during the sampling period; means for multiplying the algebraic sum by a constant K representing the ratio of the value of a Delta M modulation quantization step over the value of a PCM modulation quantization step to obtain a binary signal representing the increase or decrease of the quantized signal in pulse code modulation quantization steps; and means for adding the binary signal obtained by the above multiplication to the binary signal obtained during the sampling period Ti 1 to obtain a binary output signal corresponding to the required pulse code modulation signal.

United States Patent Deschenes et al.

[ 1 Dec. 26, 1972 [72] Inventors: Pierre A. Deschenes, Sherbrooke,

Quebec, Canada; Michel Villeret, Gisors, France [73] Assignee: Unlverslte dc Sherbrooke, :Sherbrooke, Quebec, Canada [221 Filed: June 10, 1970 [21] Appl. No.: 44,994

[52] US. Cl. ..340/347 DD, 325/38 13, 332/9, 179/15 AP [51] Int. Cl....H03k 11/00, H03k 13/00, H031: 13/24 [58] Field of Search ..325/38 B; 340/347 DD; 235/92 EV; 179/15 AP; 332/9, 11

[56] References Cited UNITED STATES. PATENTS 3,296,612 l/l967 Tornozawa "1325/38 B 3,145,292 8/ 1964- Schwaninger ..235l92 EV Primary Examiner-Daryl W. Cook Assistant Examiner-Thomas J. Sloyan I [57] ABSTRACT A system for the conversion of a delta modulation (AM) signal into a pulse code modulation (PCM) signal and vice versa. The system for the conversion of a AM modulation signal into a PCM modulation signal comprises: register means for storing an input signal consisting of n binary digits generated by a AM modulator during a time period corresponding to a normal PCM modulation sampling period T,, each binary digit representing a positive or negative AM modulation quantization step of a quantized signal; means for effecting the algebraic sum of the positive and negative quantization steps to obtain the increase or decrease of the quantized signal during the sampling period; means for multiplying the algebraic sum by a constant K representing the ratio of the value of a AM modulation quantization step over the value of a PCM modulation quantization step to obtain a binary signal representing the increase or decrease of the quantized signal in pulse code modulation quantization steps; and means for adding the binary signal obtained by the above multiplication to the binary signal obtained during the sampling period T to obtain a binary output signal corresponding to the required pulse code modulation signal.

Attorney-Raymond A. Robic 10 Claims, 32 Drawing Figures AM LIN/f 22 24 2 8 l/VPl/T ALGEBRAIC U NFL/ER PCM,- Rio/5m? ADDER M L v Mum/W 20 KMi-l PCM I 23 PCMz, DIGITAL gin/bar; Uni/W550}? PCM LIA/K SHEET UBUF I1 INPUT REGISTER 01 5| REGISTER UTPUT REGISTER REGISTER "FIGSC FlG.5d

INPUT REGISTER INPUT RESISTER 01 SI 5 A25 0 w O 0 x1 x8 A25 2 A 2 OUTPUT 9 2 REGISTER RESISTER X9 G7 G8 HG. 5Q FIG. 5F

INVENTORS Pierre A. DESCHENES Michel VILLER T SHEET UQUF 11 INPUT REGISTER OUTPUT A53 ouTPuT REGISTER REGETER (INPUT REGISTER 011 go OUTPUT Vs cs OUTPUT REGISTER A47 REGISTER INPUT 66 INPUT REGISTER RE flsTER 05 Y1 A43 Q W (36 6O Y2 L.

AH 017 Va FK a v4 Y5 OUTPUT I 60 I REGSTERjI I REGSTER INPUT FIG. 6C INPUT F/G.5F

REGISTER RE-65TH? INVE'NTORS Pierre A. DESCHENES Michel VILLER T ATTORNEY PATENTEUnaczs I972 SHEET OSOF 11 GROUP Y7-- 7o\ X8 GROUP m PIC-3.7

ATTORNEY Michel VILLERET INVENTORS Pierre A. DESCHENES RNA PATENTED DEC 26 I972 SHEET U80F 11 m Mm a T G @E G 0 T E F A Wm W w I l ll A QUANTITIZED sasw'u. DOUBLE INTEGRATION) INPUT REGISTER INVENTORIS Pierre A. DESCHENES Michel VILLERET Q PA'TENTEDUECZS I972 3 7 O7, 7 l 2 SHEET 10 0F 11 A244 -To INTEGRATOR TO OUTPUT REGBTER OF EXPANDER rue-18 FIG. 18

' CLOCK I80 I81 I82 P 7 1190 I84- 1 N80 PCM V 4 Me I LINK I A83 AM LINK XPANDER I DGTAL E DOUBLE INTEGRATGR) SHW-T COMPARATOR REL5|TER CLOCK INVENTORS Pierre A. DESCHENES Michel VILLER T PATENTED 056261972 SHEET ll 0F 11 AM LINK mm a m n. H

Tw J

m m 3m w 5 m m I45 222 4 n12 l9 :2 as

F' FWQ F T 5 X 12- O|234567B9 INVENTORS Pierre A. DESCHENES Michel VILLER T CONVERTER FROM DELTA MODULATION TO YULSE CODE MODULATION This invention relates to a system permitting the use of delta modulation (AM) in integrated telecommunication systems and, more particularly, to a digital converter for transforming AM modulation signals into pulse code modulation (PCM) signals and vice versa.

As it is commonly known, both the AM and the PCM modulation systems perform a digital transformation of an analog signal. However, the AM modulation possesses two essential characteristics which distinguish such modulation from the PCM modulation. The first characteristic is that a AM system is a closed loop system. The second characteristic isthat the information transmitted by a AM modulation system relates to a change of amplitude between two consecutive samples of an analog signal whereas a PCM modulation system transmits the quantized amplitude of each sample of the analog signal.

The encoder of a AM modulation system comprises generally a pulse generator, a modulator, an integrator and a comparator. At the input of the system, the comparator compares the instantaneous amplitude of the analog signal with the amplitude of the analog signal stored in the integrator at the time of the previous sampling and generates a positive or negative output signal depending on whether the instantaneous amplitude of the analog signal is higher or lower than the amplitude of the analog signal stored in the integrator. The output of the comparator controls the output pulses of the pulse generator which are fed to the modulator so that the modulator generates corresponding positive or negative pulses. The train of positive or negative pulses is generated in accordance with the frequency of the pulse generator which frequency is kept constant. The train of positive and negative pulses is also fed to the integrator causing the output of the integrator to rise or fall depending on the polarity of the pulses of the modulator. Two types of integration will be considered here, that is the simple integration and the double integration. In the first case, the output of the integrator consists of the sum of a series of positive or negative quantization steps depending on the positive or negative pulses of the modulator. In the second case, the output of the integrator is a series of straight line segments the slope of which is modified by each of the above pulses.

In North America, the PCM modulation system has been used for the last few years. Such system permits the transmission of twenty-four communication channels on a single telephone line, each communication channel being multiplexed with respect to time. Although a completely digital telecommunication system has been envisaged for some time due to the increasing use of the telephone lines for transmitting data (telex, facsimile, computer data), it has always proven to be more economical to build up upon the existing telephone network.

AM modulation is not generally used in North America. However, it would be advantageous to use AM modulation in telecommunication because a AM modulator is simple and inexpensive and therefore would permit the installation of one modulator at each subscriber premises. We would then have a completely digital system right from the subscriber and, with telex in particular, it would be possible to eliminate the hereintofore required separate voice channel since the voice could then be transmitted on the data channel. Such a digital system is not possible using PCM modulation because its cost is so high that it requires the use of one modulator for several subscribers. A second advantage is that the use of a AM modulator would reduce the number of subscriber lines considerably since each subscriber would be allocated a time interval in each frame grouping 24 communication channels, that is 24 subscribers could be connected to two telephone lines.

However, the insertion of a AM modulation system in a network where a PCM modulation system is already in use requires that the two systems be compatible so as to permit a subscriber belonging to a AM modulation system to communicate with another subscriber belonging to a PCM modulation system or vice-versa.

It is thereforethe object of the invention to provide a converter for directly transforming a AM modulation signal into a PCM modulation signal and vice versa without having to transform the digital signal into an analog form as an intermediate step.

it is to be noted that in order to be present at the same time on the same network, the AM modulation system and the PCM modulation system must have the same transmission characteristics. As it is already known, a seven digit binary code is used in the PCM modulation system for transmitting analog signals in a coded manner. ln addition, the sampling frequency of the PCM modulation system is 8 KHz. Consequently, in the AM modulation system, which uses a single digit binary code, a sampling frequency of 56 KHz must be used in order to be able to generate a number having sevenbinary digits during a normal PCM sampling period of 12 5 micro seconds.

The converter, in accordance with the invention, comprises:

a. register means for storing an input signal consisting of n binary digits generated by a AM modulator during a time interval corresponding to a normal pulse code modulation sampling period T,, each binary digit representing a positive or negative AM modulation quantization step of a quantized signal;

b. means for effecting the algebraic sum of said positive and negative quantization steps to obtain the increase or decrease of the quantized signal during said sampling period;

0. means for multiplying said algebraic sum by a constant K representing the ratio of the value of a AM modulation quantization step over the value of a PCM modulation quantization step to obtain a binary signal representing said increase or decrease of the quantized signal in pulse code modulation quantization steps; and

d. means for adding the binary signal obtained by said multiplication to the binary signal obtained during the preceding sampling period T to obtain a binary output signal corresponding to the required pulse code modulation signal.

The system for doing the reverse operation, that is the conversion of a PCM modulation signal into a AM modulation signal comprises:

a. first register means for storing an input signal consisting of m binary digits and representing the value x of the quantized signal at the end of a regular PCM modulation sampling period T b. a digital integrator for storing the value e of the quantized signal at the time of sampling period T c. a comparator connected to said register means and to said digital integrator" for comparing the value of the quantized signal stored in said first register means with the value of the quantized signal stored in Sai digital integrator and for generating a positive binary output signal Z 1 if x e and a negative binary output signal 2 ifx e; and

d. second register means connected to said comparator for storing said output signal which is representative of the AM modulation signal.

The invention will be further disclosed with reference to the accompanying drawings which illustrate preferred embodiments of the invention and in which:

FIG. 1 illustrates a block diagram of the transmitter of a AM modulation system;

FIG. 2 illustrates a block diagram of aconverter in accordance with the invention for converting a AM modulation signal obtained by simple integration into a PCM modulation signal;

FIG. 3 illustrates a block diagram of a converter for transforming a PCM modulation signal into a AM modulation signal;

FIG. 4 illustrates a piecewise linear characteristic used for approximating the nonlinear characteristic of a compressor suitable for use in the converter in accordance with the invention wherein the scales are indicated by binary numbers but nevertheless linear;

FIGS. 5a to 5g illustrate circuit diagrams of the compressor;

FIGS. 6a to 6f illustrate circuit diagrams of an expander for performing the reverse operation of the compressor;

FIG. 7 illustrates a simplified compressor in accordance with the invention;

FIG. 8, which appears on the same sheet as FIGS. 11 and 12, illustrates a simplified expander in accordance with the invention;

FIG. 9 illustrates a digital integrator used in the converter of the invention;

FIG. 10 illustrates the complete converter for transforming a AM modulation signal into a PCM modulation system including the compressor;

FIG. 11 illustrates a comparator used in the converter for transforming a PCM modulation signal into a AM modulation signal;

FIG. 12 illustrates a complete converter for transforming a PCM modulation signal into a AM modulation signal including the above-mentioned expander of FIG. 8, integrator of FIG. 9, and comparator of FIG. 1 1;

FIGS. 13a and 13b illustrate the principle of double integration as compared to simple integration;

FIG. 14 illustrates a digital compressor used in a converter according to a second embodiment of the invention;

FIG. 15 illustrates a complete converter for transforming a AM modulation signal into a PCM modulation system in accordance with the second embodiment of the invention;

FIG. 16 illustrates a converter for transforming a PCM modulation signal into a AM modulation signal in accordance with the second embodiment of the invention;

FIG. 17 illustrates the expander used in the converter of FIG. 16;

FIG. 18, which appears on the same sheet as FIG. 16, illustrates the comparator used in FIG. 16;

FIG. 19 illustrates a diagram of a converter used in a system having 24 channels; and

FIG. 20 illustrates the order of conversion of the 24 channels in a period T of micro seconds.

In FIG. 1, there is shown a well known AM transmitter comprising a pulse generator 10 connected to a modulator 12. A comparator 14 compares the instantaneous amplitude of an analog signal applied thereto with the output signal of an integrator 16 in which is stored the amplitude of the analog signal obtained at the time t,., of taking the preceding sample, and generates an output signal the polarity of which corresponds to the difference between the two signals applied to the comparator. Such output signal is applied to modulator l2 and controls the pulses of the pulse generator 10 applied to modulator 12 so that the modulator generates positive or negative pulses depending on the sign of the signal generated by the comparator 14. The train of positive or negative pulses is generated in accordance with the frequency of the pulse generator 10 which is kept constant. The train of positive and negative pulses is also fed to the integrator 16 which is connected in a feed-back loop to the comparator l4 and causes the output of the integrator 16 to rise or fall depending on the polarity of the pulses applied thereto. The integrator 16 may be of two types: the simple integration type and the double integration type. In the first case, the output of the integrator is the sum of a series of quantization steps which may be positive or negative in accordance with the pulses of the modulator 12. In the second case, the output of the integrator is a series of straight line segments the slope of which is modified in accordance with the pulses of the modulator. The first embodiment of the invention will disclose a converter for use with an integrator of the simple integration type. The second embodiment of the invention will disclose a converter for use with an integrator of the double integration type.

The following description of the invention will be arranged as follows:

1 converter: simple integration a characteristics b principles of operation b-l AM to PCM conversion b-2 PCM to AM conversion c description of AM to PCM converter c-l digital compressor-expander c-2 AM to PCM converter d description of PCM to AM converter d-l comparator d-2 converter 2 converter: double integration a characteristics b description of AM to PCM converter b-l digital compressor b4 AM to PCM converter c description of PCM to AM converter c-l digital expander c-2 comparator 3 operating time a time necessary for one conversion b common circuits l converter: simple integration a characteristics As commonly known, a signal may only take a definite number of values in quantized systems such as the PCM or AM modulation systems. The voltage gap between two successive values is commonly known as a quantization step and will be hereinafter designated by symbol 0-.

In the well known PCM modulation system, the signal is compressed, that is the value of the quantization steps varies depending on the instantaneous amplitude of the analog signal. In other words, the quantization steps are smaller for the weaker signals than for the stronger signals. This is done to improve the transmission of the signal by reducing the deficiencies of the so-called quantizing error which results from the difference between the instantaneous value of the analog signal and the quantized value of the same signal. In the AM modulation system under consideration, the signal does not undergo any dynamic compression which means that a pulse represents an identical increase of the analog signal no matter what the level of such signal 1s.

In the North American PCM modulation system having 24 channels, a seven binary digit code and a sampling frequency of 8 KHz is used. The normal sampling period T is 125 micro seconds. Consequently, it becomes necessary to register seven single binary digits of each communication of the AM modulation system during such time interval T using a sampling frequency of 56 KHz.

It would be desirable that the equipment used for converting a AM modulation signal into a PCM modulation signal be common to a number of channels. This problem will be studied in chapter 3 of the description. The chapters 1 and 2 disclose the principle of the invention assuming that only one AM channel is to be converted into one PCM channel or vice-versa.

Various studies have proven that, in the voice band with a sampling frequency of 56 KHz, the ratio between the maximum amplitude A of the signal at the input of a AM modulator and the amplitude of a quantization step should be in the order of ten in order to be able to follow an analog signal of a frequency of 800 Hz. To facilitate the design of the converter, it would be desirable that the ratio K of the value of a AM modulation quantization step over the value of a PCM modulation quantization step before compression be a power of 2. Since the ratio A/o- PCM 1.024, Ala AM has been chosen to be equal to 8, whereby K aAM/ o'PCM 1024/8 2".

The choice of 0' AM A/8 instead of A/ It) lowers the signal to noise ratio but increases the maximum frequency of the amplitude signal A which may be transmitted without overload distortion. As it is well known, overload distortion occurs when the quantization step is not large enough or the sampling frequency not high enough to permit the integrator output to follow rapid changes in the instantaneous amplitude of the analog signal.

b principles of operation b-l AM to PCM conversion FIG. 2 illustrates a block diagram of a AM to PCM converter in accordance with the invention. During a time interval corresponding to the regular PCM sampling period T of 125 micro seconds, the seven regularly spaced binary digits of one communication are stored in input register 20. Such binary digits consist of a number of positive signals b each represented by digital number 1 and a number of negative signals c each represented by digital number 0. The algebraic increase of the level of the quantized signal is summed in an adder 22 which determines the number a b-c of AM quantization steps that the signal has increased or decreased during the time interval T.

Since the ratio of the value of a AM quantization step over'the value of a PCM quantization step has been established as K 2', the number a of AM quantization steps is multiplied by such value K in a multiplier 24 to transform such value into a number d representing PCM quantization steps.

The output of multiplier 24 is added to the preceding PCM quantized value of the analog signal stored in a memory 26 to obtain the quantized PCM value PCM; which is stored in a memory 28.

Since the maximum number of successive binary elements of the same polarity in a simple integration AM modulator is 8, this value may be expressed by three binary digits as commonly known. Such value being multiplied by K 2 the total number of binary digits representing the amplitude of the signal stored in memory 26 will then be composed of 10 binary digits plus an llth digit representing the sign of such amplitude. Consequently, it becomes necessary to compress the 11 binary digit signal stored in memory 26 into a seven binary digit signal so as to render the output of the converter compatible with the normal PCM link. A digital compressor 29 is thus provided for that purpose.

b-2 PCM to AM conversion FIG. 3 illustrates a block diagram of a PCM to AM converter for transforming the PCM signal back into a AM signal at the receiver end of the PCM link. The signal appearing on the PCM link is expanded into an expander 30 from a seven binary digit number into an 1 1 binary digit number and fed to an input register 32. Such signal is then compared in a comparator 34 with the quantized value PCM stored in memory 36 at the time of the previous sampling period T The output of comparator 34 represents the algebraic increase or decrease of the signal since the previous sampling period and thus the AM value of the modulation signal. Such output is stored in an output register 38 and also added to the signal stored in the memory 36 in preparation for the following conversion of the PCM modulation signal into its corresponding AM value.

c description of the AM to PCM converter c-l digital compressor-expander In the general description of the converter in FIGS. 2 and 3 of the drawings, a digital compressor 29 and a digital expander 30 have been mentioned for converting an 1 1 binary digit number into a seven binary digit number and vice-versa. Such a compressor-expander is the subject of a separate application entitled PCM Digital Compandor filed concurrently by the applicant. However, a description of such a compressor-e pander will be hereinafter disclosed for the purpose of better understanding the present invention.

In telephony, a ratio of 1,000 is generally accepted between the maximum and minimum amplitudes of a signal which may be transmitted by a PCM system. For

this reason, the ratio A/o' has been chosen to be 1,024 or 2 Because of the positive and negative amplitudes of the analog signal, there will be 2,048 or 2 quantization steps in a quantized PCM system. However, such a value of a is used for weak signals only and various compression laws wherein depends on the signal level permit to keep the quantizing noise constant and acceptable by using only 2 quantization steps. As it is commonly known, the quantizing noise is caused by the quantizing error resulting from the difference between the instantaneous value of the analog signal and the quantized value of the same signal which is actually transmitted.

The principle of operation of the compressor disclosed in the present application requires the use of a digital compressor in place of the commonly known analog compressor used up until now in North Amerrca.

The compression law which will be used in the digital compressor is as follows:

wherein y output signal, x input signal, ,1. 100.

The curve obtained in following this law is approached by six straight line segments as illustrated in FIG. 4 of the accompanying drawings. However, it is to be understood that any other compression law could be used.

It is possible to code the amplitude of an analog signal in two ways:

1. the level varies between 0 and +2A and the quantization steps are numbered 1 to 2" using a number having n binary digits;

2. the level varies between +11 and -A and the quantization steps are characterized by a number having n-l binary digits representing the amplitude and an extra binary digit representing the sign or of such amplitude.

The second solution has been retained because it requires less equipment. In FIG. 4 it is only necessary to determine to which group among the six different groups (segments) belongs the binary number and on the other hand, what is its sign. This only requires 6 1 7 identification circuits. On the contrary, the first solution would have required to determine to which group among eleven groups the binary number belongs.

It is therefore necessary to transform a number .1: having 10 binary digits (the 1 l digit being the sign) into a number y having six binary (the seventh digit being the sign). The coordinates of the extremities of the segments are as follows expressed in a system using binary numbers:

However, to facilitate the distinction of the groups, eight groups have been formed as illustrated in the following Table 1 by breaking the third and fourth segments into two segments each.

TABLE 1 Intervals Group .1: element from y element from Number I 0, 111 0, 111 I1 1000. 1111 1000, 1011 111 10000, 11111 1100, 1111 IV 100000, 111111 10000, 10111 V 1000000, 1111111 11000, 11111 V1 10000000, 11111111 100000, 101111 V11 100000000, 111111111 110000, 110111 V111 1000000000, 1111111111 111000, 111111 The equations of the eight segments expressed in binary numbers are as follows:

Equations of Segments Group Group Number Number ly-=.x lly-x/lO-l-IOO llly=xl+l000 lVy-x/l00+l000 Vy=xl1000+10000 Vly-=.x/l000+10000 Vlly=xll00000+ 101000 V1lly==xll000000+110000 Referring to the above equations, it may be seen that the slopes of the various segments are: 1, 1/10, 1/100, 1/ 1000, l/100,000, 1/1,000,000.

It is to be noted that the numbers in each group before and after transformation consist of one or plural group identification digits and of plural digits which indicate the level of the number in each group. For example, if the binary digits are numbered x; to x in the order of their decreasing weights, a number x in group II is composed of seven group identification digits (0000001 and of three digits indicating the level of the number in each group (x x x The transformation of x in this group I1 is y (x/ 10) 100 which consists of four group identification digits (y, to y 0010) and two digits indicating the level in the group. This may be represented by the following equation:

x 00OOO01x x x y 00 10x Using the same convention, the transformation in the eight groups will be as follows:

The transfer of a number in each of groups I-Vlll from 10 to 6 binary elements is illustrated in the following table 2 wherein the "0 have been eliminated.

TABLE 2 Binary Ele- Group Number 3 x, x l x x r, x x

Table 2 mentioned above suggests a method for effecting the transformation. It will be necessary to:

1. identify the group to which at belongs (for example, 000000l x x x is a number in group II);

2. transfer the useful 2, 3 or 4 x, in a register having six positions;

3. store in the register the group identification digit.

The above-mentioncd operations 2 and 3 may be effected simultaneously.

If the six position register is empty before transferring any numbers into it, Table 2 indicates the elements to be placed in it.

The identification functions of each of the groups are:

Ill G f i at, 1' f, x,

FIGS. a to 5f illustrate electrical diagrams of the transfer circuits required for each group of numbers to effectuate the transformation of Table 2. Such transfer circuits include AND gates A to A and OR gates O to 0 An input register 50 and an output register 51 are illustrated for each of the groups for convenience purposes although a single input register 50 and a single output register 51 would be used in practice for all the groups.

Taking the groups separately in consecutive order, it will be seen that a number in group I the identification digits x x x x x x x of which are equal to 0 0 0 0 0 O 0 will permit gate A, to conduct to provide a digital output l to the first input of gates A A, and A to permit such gates to transfer binary digits x x x stored in the input register 50 of the compressor into the proper storage elements of the output register 51 of the compressor through OR gates O, to O in accordance with the above-mentioned Table 2. Since only one output register 51 is used in practice, only one set of OR gates 0 to 0 is needed for all the groups. The output of AND gates A to A is therefore applied to the first input of OR gates 0 to 0 The group identification digits of a number in group I] having the form 0 0 0 0 0 0 I will render gate A, conductive and thereby apply a digital signal 1 to the first input of gates A and A this causing the transfer of binary digits x and x from the input register of the compressor into the proper storage elements y and y, of the output register through the second input of OR gates 0 and 0 A number in group III having the following identification digits 0 0 0 0 0 1 will render gate A conductive and apply a digital signal l to the first input of gates A A and A through OR gate 0,, thus causing the transfer of digits x x and x., of the input register of the compressor into the proper storage elements y y, and of the output register thereof through the third input of OR gates 0 to 0 A number in group IV having the following identification digits 0 0 0 0 1 will render gate A conductive and thus apply a digital input 1 to gates A A and A thus causing the transfer of digits x x and x in the input register of the compressor into the storage elements y y, and y,, of the output register. It will be noted that the identification digits of groups III and IV are both applied through OR gate 0., to the same transfer gates A A and A Indeed, x x and x must be transferred into storage elements y y and y: in both groups, the only difference being that x, 1 in group III.

A number in group V having the following identification digits 0 0 0 1 will render gate A conductive and thus apply a digital signal l to the first input of gates A to A through OR gate 0 thus transferring digits x x x, and x in the input register of the compressor into the storage elements y y y and y of the output register of the compressor.

The output of AND gates A A and A is applied to the register through the fourth input of OR gates 0, O and 0;, respectively.

A number in group VI having the identification digits 0 O 1 will render gate A conductive thus transferring digits x x x and x into storage elements y y y and y It will be noted that the output of gates A and A are both applied through OR gate 0 to gates A to A This is because the same digits x x x and x are to be transferred into storage elements y y y and y in both groups V and VI except that in group V, x,, I.

An element in group VII having the following identification digits 0 1 will render gate A conductive thus applying a digital signal 1 to gates A A and A and transferring digits x x and X, into the storage elements y y and y through the fifth input of OR gates 0 to O A number in group VIII having the identification digit 1 will apply a digital signal 1 to gates A A and A thus transferring digits x x and x into the storage elements y y and y FIG. 5g illustrates the storage of the identification digits for each of the groups I to VIII. There is shown an OR gate 0 to which is applied the signals G G and G an OR gate 0, to which is applied the identification signals G G G and G and OR gate 0 to which is applied the identification signals G G and G such identification signals being illustrated in FIGS. 5a to 5f. One of the identification signals G, to G becomes equal to I when a number pertaining to a predetermined group occurs while the remaining identification signals remain equal to zero. For example, a number in group I causes G alone to be equal to 1 and, consequently, digits y y., and y, in the storage elements of the output register remain equal to zero.

A number in group II causes a digit 1 to be applied to OR gate 0 to change the state of y into the state I while y y, and y remain in the state zero.

A number in group III causes a digit y 1 to be stored in the output register while y, and y remain equal to zero. In addition, a digit 1 is stored in storage element y by the transfer circuit of FIG. 50.

A number in group IV causes a digit 1 to be applied to OR gate 0-, to change the state of 3 into the state 1 while y and y, remain equal to zero.

A number in group V causes a digit 1 to be applied to OR gate 0 to change the state of y into state I while y remains equal to 0. In addition, a digit 1 is stored into storage element y by the circuit of FIG. 5d.

An element in group VI causes a signal 1 to be applied to OR gate to change the state of 3 into state 1 while y remains equal to zero.

An element in group VII causes a digit 1 to be applied to both OR gates 0 and 0 thus changing the states of y., and y into state 1 while y remains equal to zero.

An element in group VIII causes a digit l to be applied to OR gates 0 O, and O to change the state of y and y into state 1.

The purpose of the digital expander is to transform a signal having seven binary elements back into a signal having 1 1 binary elements in which a is constant for all amplitudes of the signal. The compression law is opposite to that of the compressor, that is if y is the input number having six binary elements x, the output number, will have l0 binary elements. The equations are as follows:

The transformation method is the same as for the compressor. If the position register is empty before the transfer, the following Table 3 indicates the elements to be placed into it.

TABLE 3 Binary Ele- Group Number ment No. I ll III IV v w VII VIII 1 yo 2 y. Yo 3 y: in Yo Yo 4 x Y1 Y1 Y9 Y9 5 y= y: y, 6 1 Yr: Y2 Yo 7 y? Y: yr Yu 8 l y: y, 9 l y, l0 1 The identification functions of each of the groups are:

VI 6 Y5 Y4 VII 1 Y5 Y4 Ya a Ys Y4 Ya FIGS. 6a to 6f illustrate each of the transfer circuits of the expander including AND gates A to A and OR gates 0, and 0 An input register 60 and an output register 61 are illustrated for each group for convenience purposes only, although a singe input register 60 and a single output register 61 would be used in practice for all the groups. As in FIGS. 50 to 5f, OR gates 0, to 0 located at the input of the register 61 are common to at least two of the FIGS. 60 to 6f.

A number in group I the identification digits y y y 0 0 0 will render gate A conductive and apply a digital signal 1 to AND gates A A and A thus transferring digits y y, AND y of the input register 60 of the expander into the storage elements x x and x of the output register 61 of the expander. The output of AND gates A AND A is applied to the first input of OR gates O and 0 respectively.

An element in group II the identification digits y y y y: of which are 0 0 l 0 will render gate A conductive thus applying a digital signal 1 to gates A and A to transfer digits y and y, into storage elements an and x through the second input of gates 0 and 9,

A number in group III the identification digits y, y, y y of which are 0 0 l 1 will render gate A conductive thus applying a digital signal 1 to gates A A and A through OR gate 0 to transfer digits y y, and y into storage elements x x and x The output of AND gates A to A is applied to the output register through the appropriate inputs of OR gates 0 to 0,

An element in group IV the identification digits of which are 0 1 0 will render gates A. conductive thus applying a digital signal 1 to gates A A and A and transferring digits y y, and y: into storage elements x x and x It is to be noted that the identification of both groups Ill and IV is performed by the same transfer circuit through OR gate 0 It is because the same digits y y and y are transferred in both groups except that for group III, y l.

A number in group V having identification digits 0 l I will render gate A conductive thus applying a digital signal 1 to gates A to A through OR gate 0 to transfer digits y y y and y into storage elements x x x and x through OR gates 0 to 0 respectively.

An element in group VI having identification digits 10 will render gate A conductive thus applying a digital signal 1 to gates A to A and transferring digits y y y and y into storage elements y x x and x It is to be noted that groups V and VI use the same transfer circuit because in both groups the same digits y y y and y are to be transferred into x x x and x except that y 1 in group V.

An element in group Vll having identification digits 1 l 0 will render gate A conductive thus applying a digital signal 1 to gates A to A and transferring digits y y, and y into storage elements x x and x through the appropriate inputs of OR gates 0 to 0 An element in group Vlll having identification digits 1 l 1 will render gate A conductive thus applying a digital signal 1 to gates A to A and transferring digits y y and y into storage elements x x and x through the appropriate inputs of OR gates 0 to O The storage of the group identification digits is as follows;

a. a number in group I leaves storage elements x to x,, unchanged and thus equal to zero;

b. a number in group II stores a digit 1 in storage element x while x to 2: remain equal to zero;

c. a number in group III stores a digit 1 in storage element at, while leaving storage elements x to x,, equal to zero;

(I. a number in group IV stores a digit 1 in storage element .x while leaving storage elements x to 2: unchanged;

e. a number in group V stores a digit 1 in storage element x while leaving storage elements x, to x,, unchanged;

f. a number in group VI will store a digit 1 in storage element x, while leaving storage elements x and x unchanged;

g. a number in group VII will store a digit 1 in x while leaving x unchanged;

h. a number in group VIII will store a digit I in storage element x,,.

Having described a PCM compressor-expander, it will now be interesting to see how such a compressorexpander may be simplified when applied to a AM to PCM modulator in accordance with the invention or vice versa. Indeed, we have seen previously in connectionwith the general description of FIG. 2 that K, the multiplication factor of multiplier 24 was 2 This means that the first seven binary digits of the number appearing in the input register of compressor 29 will always be zero. In other words, binary digits x, x x only will be significant and digits x x x x x x, x will be equal to zero (x x x 0 0 0 O 0 0 0 Consequently, Table 2 above will be simplified as follows:

Table 4 Binary Element Number Group Number VI VII VIII 6 l I I It may be seen from Table 4 that in all groups VI, VII and VIII, the first binary digit y is equal to 0 and that the last binary digit y,, is always equal to 1. Therefore an output register having only four storage elements in sufficient to store the number. The output register connections for digit y in group VI and y in group VIII may be permanent. The transfer circuits illustrated in FIG. 5 may then be simplified and the digital compressor will look as illustrated in FIG. 7 wherein AND gates A A AND A and OR gates 0 and 0 only remain from the great number of gates in FIG. 5. In addition, input register 70 contains only three storage elements and output register 71 four storage elements. The synchronization control originating from the clock is not shown.

In operation, a number in group VI has its elements y y y and y, equal to zero and the identification thereof becomes useless.

A number in group VII having identification digits 0 1 will open gate A and apply a signal 1 to AND gate A and to OR gate 0 Such will transfer digit x into storage element y through OR gate 0 and store digit 1 into storage element y, through OR gate 0 A number belonging to group VIII having identification digit 1 will apply a digital signal 1 to the input of gates A and A to transfer digit x into storage element y and digit x into storage element y through OR gate 0 In addition, it will automatically store digit 1 into storage element y and into storage element y. through OR gate 0,.

The storage elements 71 of the compressor may be reset to zero by a clock as illustrated diagrammatically.

The expander 30 shown schematically in FIG. 6 will also be greatly simplified by the fact that digits 1: to ar are null. Consequently, the above Table 3 will look as follows.

The above Table 5 shows that a three digit output register only is required for the expander of FIG. 6. FIG. 8 illustrates that AND gates A A A A and A and OR gates 0 and 0 only are required from the great number of gates illustrated in FIG. 6. In addition, input register contains only four storage elements and output register 81 contains only three storage elements. The circuit operates as follows:

A number belonging to group VI having identification digits 1 0 is identified by y, 1 and a digit 1 is placed in the storage element x, of the output register through OR gate 0 A number belonging to group VlI having identification digits 1 l O is identified by AND gate A which applies a digit 1 to AND gate A thus transferring y, into storage element x, through OR gate 0 and 1 into storage element ar through OR gate 0 A number belonging to group VIII having identification digits 1 l l is identified by AND gate A which applies a digit 1 to AND gates A and A thus transferring digits y and y into storage elements x, and x through OR gates 0 and 0 respectively. In addition, AND gate A stores a digit 1 into storage element x c-2 AM to PCM converter Returning now to the description of the converter, the seven binary digits of one communication of a period T are successively stored into a shift register 20 (FIG. 2) having seven storage elements. After a time T (T/7), the seven binary digits are available for calculating the new PCM value of the AM signal.

This calculation must be done between time interval T- (TH) and T in order to be able to empty the shift register for the following sampling period. Otherwise, a temporary memory would have to be provided to store the digits before processing them.

It is to be noted that even if a common equipment is used for plural channels, a AM shift register 20 will still be required for each channel. Furthermore, the time interval T/7 is independent of the number of channels using the same equipment. This problem will be discussed more fully in chapter 3 of the description.

During a time T( T/7), the binary digits previously registered appear, under the control of a clock, one after the other at the output of the register 20. The input of the following element of the converter receives the seven binary digits in the order of their appearance on the PCM link at a speed which permits the processing thereof.

The operation of the AM to PCM or PCM to AM converter is very similar to the operation of a AM demodulator or modulator and, by analogy, it will be called a digital integrator.

As mentioned previously in connection with the description of FIG. 2, the three fundamental operations to be performed are: a) algebraic sum of the positive and negative pulses in a reversible counter (a b-c); b) multiplication (d Ka); and c) addition of d to the previously determined PCM, value to obtained a new PCM value.

However, it is equivalent to calculate Kb,Kc and d Kb-Kc and to algebraically add the value d to the previously determined PCM,, value. It is therefore siinpler to use a reversible counter having a capacity sufficient to store the full PCM value and to successively feed to it the +K (positive pulses) and K (negative pulses). If K is chosen to be 2 the multiplication is a simple shift of seven binary digits in the binary counter. Consequently, the operation results in the counting of pulses in a counter having only three binary storage elements 1: x x since binary elements x to ar are null.

The blocks 22, 24, 26 and 28 of FIG. 2 may then be replaced by a digital integrator such as illustrated in FIG. 9 by reference numeral 90. However, in the system chosen using ten binary digits to represent the amplitude of the signal and one digit to represent the sign, {now reduced to three binary digits (x x 'x plus one for the sign (x,,,)}, it becomes necessary to add circuits to distinguish the sign of the amplitude of the signal since the reversible counter 90 can only store the absolute value of the amplitude of the signal. In other words, a predetermined pulse to be applied to the reversible counter must be able to cause the level of the counter to raise or to fall depending on the sign of the signal already stored in it. Therefore, a circuit 91 is provided to detect the passage of the reversible counter through the value zero, this being an indication of a possible change of the sign of the level of the signal stored in the counter. To this effect, an AND gate 90 is connected to the T, terminals of storage elements x x and x and provides an output 1 when x x and x are all equal to zero. Such output 1 is applied to a delay device 92 the output of which is applied to two AND gates A and A The polarity of the following digit appearing at the output of AM register 93 will determine which one of gates A and A will conduct to store a digit representative of the sign of the signal in the reversible counter in a memory device 94 which may be a Simple i 19p e- ..,examp sz ifzaa=.. (p tive signal), gate A will conduct to store a digit 1 in storage element x of memory device 94. If on the other hand xAM= 0 (negative signal), a signal 1 will be applied from A M to A92 to store a dig it1 inten of memory device 94.

Delay device 92 is used to prevent an early operation of memory device 94 by delaying the opening of gates A and A92 until after the digit an which was brought the level of the reversible counter to 0 has disappeared from the input of gates A and A A second circuit 95 is provided to determine if the absolute value of the level of the counter 90 should rise or fall depending on the sign of the binary digit to be stored in the register and on the sign of the signal already stored in it. Such a circuit comprises two AND gates A and A responsive to flip-flop device 94 and to the signal at the output of register 93. In addition, an OR gate 0 is connected to the output of AND gates A and A and to the output of delay device 92.

In operation, if xAM and x are both equal to 1, A provides a digital output l to the terminal of the reversible counter to increase the level of the signal in the counter. If, on the other hand x =0 and x10 1, the output of gates A and A, will be zero. Such value zero will he inverted by inverter 96 and a digital signal 1 will be applied to the negative terminal of the counter to lower the level of the signal stored into it.

Let us assume now that the level of the signal in the counter 90 has decreased to a level below zero and that circuit 91 has caused a signal x 0 to be stored in memory 94. If a signal x =O appears at the output of register 93, gate A the inputs of which are respon sive to I AM and 35 will provide a digital signal 1 to the terminal lof the reversible counter to increase the level of the signal stored into the counter. In other words, if a negative signal is already stored into the counter, the appearance of a negative pulse at the output of register 93 will cause the absolute value of the level of the signal in the reversible counter to rise. If, on he cinema....as nawe PPwS at the Output of register 93, gates A and A, will not conduct and a digital signal 0 will appear at the output of OR gate 0 Such digital signal will be inverted by inverter 96 to a digital signal 1 which is applied to the negative terminal of the reversible counter 90 to decrease the level of the signal already stored in the counter.

The first pulse applied to the reversible counter 90 following the passage of the level of the counter to zero must always be applied to terminal thereof in order to store such pulse in the counter. For this reason, the output s of delay device 92 is also applied to OR gate 0 ttqsssitargsjt yi si n Me f ew ns a et rn of the counter to level zero with x 0 would cause a digital signal 1 to be applied to the terminal of the counter which cannot be done. Similarly, a negative signal x Q when the level of the counter is zero and .x =1 would cause a decrease of the level of the counter which is impossible. Therefore, the digital output 1 appearing at the output of the device 92 is applied to the positive terminal of counter 90 to cause the counter to always raise its level by one digit upon reception of the following digit of register 93 after the passage of the counter by the value zero. The above operation of the digital integrator circuit may be summarized by the following logic function:

The above disclosed circuits 9] and 95 of the digital integrator are needed because of the simplification of the compressor. If a number having four binary digits have been chosen to represent the amplitude of a signal varying between 0 and +2A instead of using three binary digits for the amplitude plus a fourth digit for the sign, the compressor would have been much more complex but a reversible counter having four storage elements would have been sufficient without having to provide circuits 91 and 95. It is obvious that in both cases the principle of operation is the same.

The circuit of the compressor of FIG. 7 and the circuit of the integrator of FIG. 9 are assembled together in FIG. 10 to produce a complete AM to PCM converter. However, the synchronization control originating from the clock is not shown.

In order to more clearly see how the two circuits are interconnected, the same reference characters have been used. In addition, the seven storage elements of shift register 93 have been shown together with a shift control connection originating from a clock in a known manner. It may also be seen that binary digit y, which is always equal to zero as well as binary digit y which is always equal to l have been shown schematically as being permanent in output register 71. It is also to be understood that such a register is known in the art and may be composed, for example, of flip-flop devices.

It is to be noted that if the normal PCM code was composed of seven binary digits representing the am- 

1. A system for the conversion of a delta modulation signal generated by a delta modulator into a pulse code modulation signal comprising: a. register means for stOring an input signal consisting of a number n of binary digits generated by said delta modulator during a time period corresponding to a normal pulse code modulation sampling period Ti, said number n being greater than zero and each binary digit representing a positive or negative delta modulation quantization step of a quantized signal; b. means for effecting the algebraic sum of said positive and negative quantization steps to obtain the increase or decrease of the quantized signal during said sampling period; c. means for multiplying said algebraic sum by a constant positive integer K representing the ration of the value of a delta modulation quantization step over the value of a pulse code modulation quantization step to obtain a binary signal representing said increase or decrease of the quantized signal in pulse code modulation quantization steps; d. means for adding the binary signal obtained by said multiplication to the binary signal obtained during the preceding sampling period Ti 1 to obtain a m bit binary output signal corresponding to the regular pulse code modulation signal; and e. a digital compressor for receiving said output signal for transforming said output signal to a q bit pulse code modulation signal, where q is less than m.
 2. A system as defined in claim 1, wherein elements b), c) and d) are combined in ''''a digital integrator'''' including a reversible binary counter capable of storing said binary output signal, said reversible counter being fed with an input signal corresponding to K positive or K negative pulses representing the increase or decrease of the quantized signal in pulse code modulation quantization steps.
 3. A system as defined in claim 2, wherein the maximum number of Delta M quantization steps of the quantized input signal is 23 and may be represented by a three binary digit number plus a fourth digit for the sign, and wherein K is equal to 27, whereby said binary output signal is a number comprising ten binary digits representing the amplitude of the quantized signal and an 11th digit representing the sign of the quantized signal and in which the seven less significant digits are null, and wherein said reversible binary counter comprises three binary storage elements capable of storing the absolute value of the three most significant digits of said output signal and an additional storage element for storing the sign thereof.
 4. A system as defined in claim 3, wherein said ''''digital integrator'''' comprises a first gate circuit responsive to the sign of said input signal and to the output signal stored in said reversible counter for detecting a change of sign of the output signal stored in the binary reversible counter and for storing said change of sign in said additional storage element, and a second gate circuit responsive to both said additional storage element and to the sign of the input signal to be stored in said reversible counter for causing the level of said reversible counter to rise or fall accordingly.
 5. A system as defined in claim 3, further comprising circuit means for transforming the number having three significant binary digits stored in the storage elements of said reversible counter and representing the amplitude of the output signal, and the additional binary digit stored in said additional storage element of said reversible counter and representing the sign of the amplitude of said output signal into a number having six binary digits representing the amplitude of the output signal and a seventh binary digit representing the sign of the amplitude of the output signal to produce a seven binary digit number corresponding to the normal pulse code modulation code number.
 6. A system as defined in claim 5, wherein said transforming means comprises an output register having storage elements for storing said six binary digit number representing the amplitude Of the output signal, a first gate circuit responsive to predetermined combinations of binary digits in the storage elements of said reversible counter for identifying the group to which said binary digit number belongs and for storing the digits identifying said group into predetermined storage elements of said output register, a second gate circuit interconnecting predetermined storage elements in said binary reversible counter to predetermined storage elements of said output register and responsive to said first gate circuit for transferring the binary digits relating to the level of said binary digit number into the predetermined storage elements of said output register.
 7. A system as defined in claim 1, for use with a delta modulator of the double integration type wherein the maximum number of consecutive positive or negative pulses of said input signal is eight, wherein the maximum number of Delta M quantization steps is 25, and wherein K equals 25 thus rendering the five less significant digits of the binary output signal null, said elements b), c) and d) being combined in a ''''digital integrator'''' comprising a first stage of integration including a first reversible counter capable of storing said maximum number of consecutive positive or negative pulses and a second stage of integration including a second reversible counter capable of storing the five most significant binary digits of the output signal, and a linking circuit for transferring the binary digits stored into the first integration stage into the second integration stage.
 8. A system as defined in claim 7, wherein said linking circuit comprises an auxiliary counter, a comparator to which is applied the output of said first integration stage and the output of said auxiliary counter, and a pulse generator responsive to the output of said comparator for storing the required binary digits into said second integration stage.
 9. A system as defined in claim 7, further comprising circuit means for transforming said number having five significant binary digits stored into the five storage elements of said second reversible counter and representing the amplitude of the output signal and an additional binary digit representing the sign of the amplitude into a number having six binary digit representing the amplitude of the output signal and a seventh binary digit representing the sign of the amplitude to produce a seven binary digit number corresponding to the normal pulse code modulation code.
 10. A system as defined in claim 9, wherein said transforming means comprises an output register having six storage elements for storing the amplitude of the signal, a first gate circuit responsive to predetermined combinations of binary digits in the storage elements of said second binary counter for identifying the group to which said five binary digits belong and for storing the digits identifying said group into predetermined storage elements of said output register, a second gate circuit interconnecting predetermined storage elements in said second reversible counter to said output register and responsive to said first gate circuit for transferring the binary digits relating to the level of said five binary digit number into the predetermined storage elements of said output register. 